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multisupply supervisor/sequencer with margining control and auxiliary adc inputs preliminary technical data ADM1066 rev. prl information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2003 analog devices, inc. all rights reserved. features 10 supply fault detectors enabli ng supervision of supplies to better than 1% accuracy 5 selectable input attenuators allow supervision: supplies up to 14.4 v on vh supplies up to 6 v on vp1-4 5 dual function inputs vx1-5: high impedance input to supply fault detector with thresholds between 0.573 v and 1.375 v general-purpose logic input device powered by the highest of vp1C4, vh 2.048 v reference (0.3%) on refout pin 12-bit adc for read-back of all supervised voltages reference input, refin2 input options: driven directly from refout more accurate external reference for improved adc performance 6 voltage output 8-bit dacs (0.300 v to 1.551 v) 2 auxiliary (single- ended) adc inputs 10 programmable output drivers (pdo1-10) open collector with external pull-up push-pull output, driven to vddcap or vpn open collector with weak pull-up to vddcap or vpn internally charge pumped high drive for use with external n-fet (pdo1C6 only) sequencing engine (se) implements state machine control of pdo outputs: state changes conditional on input events can enable complex control of boards power up and power down sequence control fault event handling interrupt generation on warnings watchdog function can be integrated in se program software control of sequencing through smbus user eeprom: 256 bytes industry standard 2-wire bus interface (smbus) guaranteed pdo low with vh, vpn = 1.2 v 40-lead lfcsp and 48-lead tqfp packages functional block diagram figure 1. applications central office systems servers/routers multivoltage system line cards dsp/fpga supply sequencing in circuit testing of margined supplies general description the ADM1066 is a configurable supervisory/sequencing device which offers a single chip solution for supply monitoring and sequencing in multiple supply systems. in addition to these functions the ADM1066 integrates a 12-bit adc and six 8-bit voltage output dacs. these circuits can be used to implement a closed loop margining system. this enables supply adjustment by altering either the feedback node or reference of a dc/dc converter using the dac outputs. (continued on page 3)
ADM1066 preliminary technical data rev. prl| page 2 of 32 table of contents general description ......................................................................... 3 ADM1066 specifications ................................................................. 4 pin configurations and functional descriptions ........................ 7 absolute maximum ratings............................................................ 8 thermal characteristics .............................................................. 8 esd caution.................................................................................. 8 typical performance characteristics ............................................. 9 ADM1066 inputs ............................................................................ 12 powering th e ADM1066 ............................................................ 12 supply supervision..................................................................... 13 input comparator hysteresis.................................................... 13 input glitch filtering ................................................................. 13 supply supervision with vxn inputs...................................... 14 supply supervision using the adc ......................................... 14 vxn pins as digital inputs ....................................................... 15 ADM1066 outputs......................................................................... 16 ADM1066 sequencing engine...................................................... 18 warnings...................................................................................... 18 sw flow-unconditional jump ................................................. 18 end of step detector .................................................................. 19 monitoring fault detector ........................................................ 19 timeout detector ....................................................................... 20 closed loop supply margining................................................ 20 writing to the dacs .................................................................. 21 choosing the size of the feedback resistor ........................... 21 dac limiting/other safety features ...................................... 21 communicating with the ADM1066 ........................................... 22 configuration download at power-up................................... 22 updating the configuration of the ADM1066....................... 22 updating the sequencing engine of the ADM1066 .............. 23 internal registers of the ADM1066 ......................................... 23 ADM1066 eeprom.................................................................. 23 serial bus interface..................................................................... 24 identifying the ADM1066 on the smbus .............................. 24 general smbus timing............................................................ 24 smbus protocols for ram and eeprom .............................. 24 ADM1066 write operations................................................. 26 ADM1066 read operations................................................... 27 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 30 revision history revision prl: update of specifications revision prk: preliminary version
preliminary technical data ADM1066 rev. prl| page 3 of 32 general description (continued from page 1) the supply margining can be performed, with a minimum of external components. the margining loop can be used at in circuit testing of a board during production (to verify the boards functionality at say ?5% of nominal supplies), or can be used dynamically to accurately control the output voltage of a dc/dc converter. the device also provides up to ten programmable inputs for monitoring under, over, or out-of-window faults on up to ten supplies. in addition, ten programmable outputs are provided. these can be used as logic enables. six of them can also provide up to a +12v output for driving the gate of an n- channel fet which may be placed in the path of a supply. the logical core of the device is a sequencing engine. this is a state machine based construction, providing up to 63 different states. this enables very flexible sequencing of the outputs, based on the condition of the inputs. the device is controlled via configuration data which can programmed into an eeprom. all of this configuration can be programmed using an intuitive gui based software package provided by adi. figure 2. detailed block diagram
ADM1066 preliminary technical data rev. prl | page 4 of 32 ADM1066 specifications 1 vh = 3.0 v to 14.4 v, vpn = 3.0 v to 6.0 v 2 , t a = ?40c to 85c, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments power supply arbitration vh, vpn 3.0 v min. of vddcap=2.7v required vp 6.0 v max vddcap= 5.1v, typical vh 14.4 v vddcap = 4.75v vddcap 4.75 5.4 v any vpn =6.0v, vh = 14.4v power supply supply current, i vh , i vpn (dacs, and adc off) 3.5 8 ma vddcap=4.75v, no pdo fet drivers on, no loaded pdo pullups to vddcap additional currents all pdo fet drivers on 1 ma vddcap=4.75v, (l oaded with 1a), no pdo pullups to vddcap. current available from vddcap 2 ma max. additional load that can be drawn from pdo pullups to vddcap dacs supply current 2 ma 6 dacs on with 100a max load on each adc supply current 1 ma running round robin loop eeprom erase current 10 ma 1ms duration only. vddcap=3v supply fault detectors vh pin input impedance 22 k? from vh to gnd input attenuator error 0.1 % mid range 0.2 % high range detection ranges high range 6 14.4 v mid range 2.5 6 v vpn pins input impedance 50 k? from vpn to gnd input attenuator error 0.1 % low and mid ranges detection ranges mid range 2.5 6 v low range 1.25 3 v ultra low range 0.573 1.375 v no input attenuation error vx pins input impedance 1 m? detection ranges ultra low range 0.573 1.375 v no input attenuation error absolute accuracy 1 % input attenuator error + vref error + dac non linearity + comparator offset error threshold resolution 8 bits digital glitch filter 0 100 s 8 filter length options analog to digital converter signal range 0 v refin v the adc can convert signals presented to the vh, vpn and vx_gpin pins.vpn and vh in put signals are attenuated depending on selected range. a signal at the pin corresponding to the selected range will be between 0.573v and 1.375v at the adc input. input reference voltage on refin pin, vrefin 2.048 tbd v vddcap=2.7v
preliminary technical data ADM1066 rev. prl| page 5 of 32 parameter min typ max unit test conditions/comments tbd v vddcap=4.75v resolution 12 bits inl 2.5 lsb end-point corrected, v refin =2.048v gain error 0.05 % v refin = 2.048v offset error 2 lsb v refin = 2.048v input noise 0.25 lsb rms direct input (no attenuator) buffered voltage output dacs resolution 8 bits code 80h output voltage 6 dacs are individually selectable to be centered on one of four output voltage ranges range 1 0.6 v range 2 0.8 v range 3 1 v range 4 1.25 v mid code error 6 mv output voltage range 601.25 mv same range independent of centre point lsb step size 2.36 mv inl 1 lsb end point corrected dnl 0.4 lsb gain error 1 % max load current (source) 100 a max load current(sink) 100 a max load capacitance 50 pf settling time into 50pf load 3 2 s load regulation 2.5 mv per ma psrr 60 db dc 40 db 100mv step in 20ns with 50pf load reference output reference output voltage 2.043 2.048 2.054 v no load max load current (source) 200 a max load current (sink) 100 a min load capacitance 100 nf cap required for decoupling, stability load regulation 2 mv per 100a psrr 60 db dc programmable driver outputs high voltage (charge pump) mode (pdo1-6) output impedance 500 k? v oh 11 12.5 14 v i oh =0 10.5 12 v i oh =1a i outavg 20 a 2v < v oh < 7v standard (digital output mode (pdo1-10)) v oh 3 2.4 v v pu (pullup to vddcap or v pn ) = 2.7v, i oh = 0.5ma 4.75 v v pu to v pn = 6.0v, i oh = 0ma v pu ?0.3 v v pu < = 2.7v, i oh = 0.5ma v ol 0 0.75 v i ol = 20ma i ol 20 ma max sink current per pdo pin i sink 60 ma max total sink for all pdos r pullup 20 k? internal pullup
ADM1066 preliminary technical data rev. prl | page 6 of 32 parameter min typ max unit test conditions/comments i source (vpn) 2 ma current load on any vpn pull- ups (ie) total source current available through any number of pdo pull-up switches configured on to any one tristate output leakage current 10 a v pdo = 14.4v oscillator frequency 100 khz all on- chip time delays derived from this clock digital inputs (vxn,a0,a1) input high voltage, v ih 2.0 v max. v in =5.5v input low voltage, v il 0.8 v max. v in =5.5v input high current, i ih ?1 a vin= 5.5v input low current, i il 1 a vin= 0 input capacitance tbd pf programmable pulldown current, i pulldown 20 a vddcap=4.75. t a =25 0 cif known logic state required serial bus digital inputs (sda,scl) input high voltage, v ih 2.0 v input low voltage, v il 0.8 v output low voltage, v ol 0.4 v i out = -3.0ma serial bus timing clock frequency, f sclk 400 khz bus free time, t buf 4.7 s start setup time, t su;sta 4.7 s start hold time, t hd;sta 4 s scl low time, t low 4.7 s scl high time, t high 4 s scl, sda rise time, t r 1000 s scl, sda fall time, t f 300 s data setup time, t su;dat 250 ns data hold time, t hd;dat 300 ns 1 these are pre-release specifications and subject to change. 2 at least one of the vh, vp1-4 pins must be 3.0v to maintain device supply on vddcap. 3 guaranteed by characterization. 4 guaranteed by design.
preliminary technical data ADM1066 rev. prl| page 7 of 32 pin configurations and functional descriptions figure 3. lfcsp pin configuration figure 4. tqfp pin configuration table 2. pin functional descriptions pin no. lfcsp tqfp mnemonic description 1 nc no connection. 1C5 2-6 vx1C5 high impedance inputs to supp ly fault detectors. fault thre sholds can be set at between 0.573 v and 1.375 v. alternatively these pins ca n be used as general purpose digital inputs. 6C9 7-10 vp1C4 low voltage inputs to supply faul t detectors. three input ranges can be set by altering the input attenuation on a potential divider connect ed to these pins, the output of which connects to a supply fault detector; these allow thresholds between 2.5 v to 6v, 1.25 v to 3 v and 0.573 v to 1.375 v. 10 11 vh high voltage input to supply faul t detectors. three input ranges can be set by altering the input attenuation on a potential divider connected to this pin, the output of which connects to a supply fault detector; these al low thresholds between 6v to 14.4v, 2.5 v to 6 v and 1.25 vto 3 v. 12-13 nc no connection. 11 14 agnd ground return for input attenuators. 12 15 refgnd ground return for on-chip reference circuits. 13 16 refin reference input for adc, nominally 2.048v. 14 17 refout 2.048 v reference output. 15C20 18-23 dac1C6 voltage output dacs. defa ult to high impedance at power-up. 24-25 nc no connection. 21C30 26-35 pdo10C1 programmable output drivers. 36-37 nc no connection. 31 38 pdognd ground return for output drivers 32 39 vccp central charge pump voltage of 5.25v. a reserv oir capacitor must be connected between this pin and gnd. 33 40 a0 logic input which sets the sevent h bit of the smbus interface address. 34 41 a1 logic input which sets the sixt h bit of the smbus interface address. 35 42 scl smbus clock pin. open drain output requiring external resistive pull-up. 36 43 sda smbus data i/o pin. open drain o utput requiring external resistive pull-up. 37 44 aux2 auxiliary, single ended, adc input 38 45 aux1 auxiliary, single ended, adc input 39 46 vddcap device supply voltage. linearly regulated from the highest of the vp1-4,vh pins and clamped to a maximum of 4.75v 40 47 gnd supply ground. 48 nc no connection.
ADM1066 preliminary technical data rev. prl | page 8 of 32 absolute maximum ratings table 3. parameter rating voltage on vh pin 17 v voltage on vp pins 7 v voltage on any other input ?0.3 v to +6.5 v input current at any pin 5 ma package input current 20 ma maximum junction temperature (t jmax ) 150c storage temperature range ?65c to +150c lead temperature, soldering vapor phase, 60 s 215c esd rating all pins 2000 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics 40-pin lfcsp package: ja = tbdc/w esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data ADM1066 rev. prl| page 9 of 32 typical performance characteristics figure 5. dnl for on- chip 12- bit adc figure 6. inl for on- chip 12- bit adc figure 7. vvddcap vs. vvh and vvp1 figure 8. idd vs. vvp1 (supply) figure 9. ivp1 vs. vvp1 (not supply) figure 10. idd vs. vvh
ADM1066 preliminary technical data rev. prl | page 10 of 32 figure 11. ivh vs. vvh (not supply) figure 12. ivx1 vs. vvx1 figure 13. percentage deviation in vthresh vs. temperature 10 10 . 5 11 11. 5 12 12 . 5 13 13 . 5 14 -40 -25 -10 5 20 35 50 65 80 temperat ure ( o c) 1ua load 0ua load figure 14. pdo output (fet drive mode) vs. temperature 0 0.5 1 1. 5 2 2.5 3 3.5 4 4.5 00.5 11.52 iload ( ma) v vp1 =3 . 3 v v vp1 =5 v figure 15. pdo output (strong pull-up to vp1) vs. load curr. 0 0.5 1 1. 5 2 2.5 3 3.5 4 4.5 0 10 203040 iload ( ua) v vp1 =3 . 3 v v vp1 =5 v figure 16. pdo output (weak pull-up to vp1) vs. load current
preliminary technical data ADM1066 rev. prl| page 11 of 32 figure 17. pdo output (strong pull-down) vs. load current 0 0.2 0.4 0.6 0.8 1 1. 2 1. 4 1. 6 1. 8 2 0 20 406080 iload ( ua) figure 18. pdo output (weak pull-down) vs. load current figure 19. oscillator frequency vs. temperature figure 20. vccp vs. load current figure 21. vxn (digital input mode) threshold vs. temperature
ADM1066 preliminary technical data rev. prl | page 12 of 32 ADM1066 inputs powering the ADM1066 the ADM1066 is powered from the highest voltage input on either the positive only supply inputs (vpn) or the high voltage supply input (vh). the same pins are used for supply fault detection (discussed below) . a v dd arbitrator on the device chooses which supply to use. the arbitrator can be considered an oring of five ldos together. a supply comparator chooses which of the inputs is highest and selects this one to provide the on- chip supply. there is minimal switching loss with this architecture (~0.2v), resulting in the ability to power the ADM1066 from a supply as low as 3.0v. note that the supply on the vxn pins cannot be used to power the device. an external cap to gnd is required to decouple the on chip supply from noise. this cap should be connected to the vddcap pin, as shown in figure 22. the cap has another use during brown outs (momentary loss of power). under these conditions, where the input supply, vpn or vh, dips transiently below v dd , the synchronous rectifier switch immediately turns off so that it doesnt pull v dd down. the v dd cap can then act like a reservoir and keep the device active until the next highest supply takes over the powering of the device. 10f is recommended for this reservoir/decoupling function. note that in the case where there are two or more supplies within 100mv of each other, the supply which takes control of v dd first will keep control (e.g) if vp1 is connected to a 3.3v supply, then v dd will power up to approximately 3.1v through vp1. if vp2 is then connected to another 3.3v supply, vp1 will still power the device, unless vp 2 goes 100mv higher than vp1. figure 22. vdd arbitrator operation the ADM1066 has ten programmable inputs. five of these are dedicated supply fault detectors (sfds). these dedicated inputs are called vh and vp1-4 by default. the other five inputs have dual functionality. they can either be used as supply fault detectors, with similar functionality to vh and vp1-4, or they can be used as cmos/ttl compatible logic inputs to the devices. thus, the ADM1066 can have up to ten analog inputs, a minimum of five analog inputs and five digital inputs, or a mix. note that if an input is used as an analog input, it cannot be used as a digital input. thus, a configuration requiring ten analog inputs would have no digital inputs available. table 4 shows the details of each of the inputs. table 4. input functions, thresholds and ranges input function voltage range max hystere sis voltage resolution glitch filter vh high v analog input 2. 5v to 6v 425mv 13.7mv 0-100s 4.8v to 14.4v 1.16v 37.6mv 0-100s vpn positive analog input 0.573 to 1.375v 97.5mv 3.14mv 0-100s 1.25 to 3v 212mv 6.8mv 0-100s 2.5 to 6v 425mv 13.7mv 0-100s vxn high z analog input 0.573 to 1.375v 97.5mv 3.14mv 0-100s digital input 0 to 5v n/a n/a 0-100s
preliminary technical data ADM1066 rev. prl| page 13 of 32 figure 23. supply fault detector block supply supervision the ADM1066 has up to ten supply fault detectors (sfds) on its ten input channels. these are highly programmable reset generators. this enables the supervision of up to ten supply voltages. these supplies can be as low as 0.573v and as high as 14.4v. the inputs can be configured to detect an undervoltage fault (where the input voltage droops below a preprogrammed value), an overvoltage fault (where the input voltage rises above a preprogrammed value) or an out-of-window fault (undervoltage or overvoltage). the thresholds can be programmed to 8-bit resolution in registers provided in the ADM1066. this translates into a voltage resolution which is dependent on the range selected. the resolution is given by 255 rang theshold size step = thus, if the high range were selected on vh, the uv and ( ) mv 6 37 255 v 8 4 v 4 14 . . . = ? listed below are the upper and lower limit of each range available, the bottom of each range and the range itself. the threshold value required is given by ( ) b r t v 255 n v v x + = table 5. voltage range v b (v) v r (v) 0.573 to 1.375v 0.573 0.802 1.25 to 3v 1.25 1.75 2.5 to 6v 2.5 3.5 4.8 to 14.4v 4.8 9.6 where: v t is the desired threshold voltage (uv or ov). v r is the voltage range. n is the decimal value of the 8-bit code. v b is the bottom of the range. reversing the equation, the code for a desired threshold is given by ( ) r b t v v v 255 n ? = for example, if the user wishes to set a 5v ov threshold on vp1, the code to be programmed in the ps1ovth register (discussed in an-698) would be ( ) 5 3 5 2 5 255 n . . ? = ( ) 6 xb 0 or bin 10110110 182 n thus , = input comparator hysteresis the uv and ov comparators shown in figure 22 are always looking at vpn. in order to avoid chattering (multiple transitions when the input is very close to the set threshold level), these comparators have digitally programmable hysteresis. the hysteresis can be programmed up to the values shown in table 4. the hysteresis is added after a supply voltage goes out of tolerance. thus, the user can program how much above the uv threshold the input must rise again before a uv fault is de-asserted. similarly, the user can program how much below the ov threshold an input must fall again before an ov fault is de-asserted. the hysteresis figure is given by 255 n v threst r = hyst v where: v hyst is the desired hysteresis voltage. n thresh is the decimal value of the 5 bit hysteresis code. note that n thresh has a maximum value of 31. the maximum hysteresis for each of the ranges is quoted in table 4. input glitch filtering the final stage of the sfds is a glitch filter. this block provides time domain filtering on the output of the sfd comparators. this allows the user to remove any spurious transitions (such as supply bounce at turn-on). the glitch filter function is additional to the digitally programmable hysteresis of the sfd comparators. the glitch filter timeout is programmable up to 100s. the functionality of the block is best explained using an example. a glitch filter timeout of 100s means that pulses which appear on the input of the glitch filter block and are less than 100_s in duration will be prevented from appearing on the output of the glitch filter block. any input pulse which is longer in duration than 100s will appear on the output of the glitch filter block. the output will be delayed with respect to the input by 100s. the filtering process is shown in figure 24.
ADM1066 preliminary technical data rev. prl | page 14 of 32 figure 24. input glitch filter function supply supervision with vxn inputs the vxn inputs have two functions. they can either be used as supply fault detectors or as digital logic inputs. when selected to be an analog (sfd) input, the vxn pins have very similar functionality to the vh and vpn pins. the major difference is that the vxn pins have only one input range, 0.573v to 1.375v. therefore, these inputs can only supervise very low supplies directly. however, the input impedance of the vxn pins is high, allowing an external resistor divide network to be connected to the pin. thus, any supply can be potentially divided down into the input range of the vxn pin and supervised. this enables other supplies such as +24v, +48v, ?5v to be monitored by the ADM1066. an additional supply supervision function is available when the vxn pins are selected as digital inputs. in this case, the analog function is available to be used as a second detector on each of the dedicated analog inputs, vp1-4 and vh. the analog function of vx1 is mapped to vp1, vx2 is mapped to vp2 etc. vx5 is mapped to vh. in this case, these sfds can be viewed as a secondary or warning sfd. these secondary sfds are fixed to the same input range as the primary sfd. they are used to indicate warning levels rather than failure levels. this allows faults and warnings to be generated on a single supply using only one pin. for example, if vp1 was set to output a fault if a 3.3v supply drooped to 3.0v, vx1 could be set to output a warning at 3.1v. warning outputs are available for readback from the status registers. they are also ored together and fed into the sequencing engine (se), allowing warnings to generate interrupts on the pdos. thus, in the example above, if the supply drooped to 3.1v, a warning would be generated, and remedial action could be taken before the supply dropped out of tolerance. supply supervision using the adc a further level of supervision is provided by the on- chip 12 bit adc. the adc has a twelve channel analog mux on the front end. the twelve channels are the ten sfd inputs and two auxiliary (single ended) adc inputs. any or all of these inputs can be selected to be read in turn by the adc. the circuit controlling this operation is called the round robin. the round robin can be selected to run through its loop of conversions just once or continuously. averaging is also provided for each channel. in this case the round robin will run through its loop of conversions sixteen times before returning a result for each channel. at the end of this cycle the results are all written to the output registers. limit registers are provided on the ADM1066 which the user can program to a maximum or minimum allowable threshold. exceeding the threshold generates a warning which can be read back from the status registers or inputted into the se to determine what sequencing action the ADM1066 should take. only one register is provided for each input channel so an uv or ov threshold but not both can be set for a given channel. the round robin can be enabled either via an smbus write, or can be programmed to turn on in any state in the se program, for instance it can be set to start once a powerup sequence is complete and all supplies are known to be within expected tolerance limits. note that there is a latency built into this supervision which is dictated by the conversion time of the adc. with all twelve channels selected the total time for the round robin operation (averaging off) will be approximately 6ms (500s per channel selected). supervision using the adc, therefore, does not provide the same real time response as the sfds. the adc samples single-sided inputs with respect to the agnd pin. a 0v input gives out code 0 and an input equal to the voltage on refin gives out full code (4095 (dec)) the inputs to the adc come directly from the vxn pins and from the back of the input attenuators on the vpn and vh pins, as shown in figure 25 and 26 below. 12- bit adc 2.048v vref vxn digitized voltage reading no attenuation figure 25. adc reading on vxn pins
preliminary technical data ADM1066 rev. prl| page 15 of 32 12- bit adc 2.048v vref vpn/vh digitized voltage reading attenuation network (depends on range selected) figure 26. adc reading on vxn pins the voltage at the input pin can be derived from the following equations:- v nfactor attenuatio adccode v 048 . 2 4095 = the adc input voltage range for each of the sfd input ranges is given in table 6 below. table 6. sfd input range attenuation factor adc input voltage range 0.573 to 1.375v 1 0 to 2.048v 1.25 to 3v 2.181 0 to 4.46v 2.5 to 6v 4.363 0 to 6.0v* 4.8 to 14.4v 10.472 0 to 14.4v* * the upper limit is the absolute maximum allowed voltage on these pins. it is normal to supply the reference to the adc on the refin pin simply by connecting the refout pin to the refin pin. refout provides a 2.048v reference. as such, the supervising range covers less that half of the normal adc range. it is possible to provide the adc with a more accurate external reference for improved read-back accuracy. also, it is possible to connect supplies to the input pins purely for adc read-back even though they may go above the expected supervisory range limits (though not above 6v as this would violate the absolute maximum ratings on these pins). for instance a 1.5v supply connected to the vx1 pin would correctly read out as an adc code of approximately 3/4 full scale but would always sit above any supervisory limits that could be set on that pin. it is not possible to set refin to higher than 2.048v. vxn pins as digital inputs as outlined previously, the vxn inputs pins on the ADM1066 have dual functionality. the second function is as a digital input to the device. thus, the ADM1066 can be configured to have up to five digital inputs. these inputs are ttl/cmos compatible. standard logic signals can be applied to the pins: reset from reset generators, pwrgood signals, fault flags, manual resets, and so on. these signals are available as inputs to the se, and so can be used to control the status of the pdos. the inputs can be configured to detect either a change in level or an edge. when configured for level detect, the output of the digital block is simply a buffered version of the input. when configured for edge detect, once the logic transition is detected, a pulse of programmable width is outputted from the digital block. the width is programmable from 0s to a maximum of 100s. the digital blocks feature the same glitch filter function available on the sfds. this enables the user to ignore spurious transitions on the inputs. for example, the filter can be used to debounce a manual reset switch. when configured as digital inputs, each of the vxn pins has a weak (10a) pull-down current source available for placing the input in a known condition, even if left floating. the current source, if selected, weakly pulls the input to gnd. figure 27. vxn digital input function
ADM1066 preliminary technical data rev. prl | page 16 of 32 ADM1066 outputs supply sequencing through configurable output drivers supply sequencing is achieved with the ADM1066 by using the programmable driver outputs (pdos) on the device as control signals for supplies. the output drivers can either be used as logic enables or as fet drivers. the sequence in which the pdos are asserted (and, thus, the supplies are turned on) is controlled by the sequencing engine (se). the se determines what action is to be taken with the pdos based on the condition of the inputs of the ADM1066. thus, the pdos can be set up to assert when the sfds are in tolerance, the correct input signals are received on the vxn digital pins, there are no warnings from any of the inputs of the device, and so on. the pdos can be used for a number of functions: the primary function is to provide enable signals for ldos or dc/dc convertors which generate supplies locally on a board. the pdos can also be used to provide a power_good signal when all of the sfds are in tolerance or provide a reset output if one of the sfds goes out of spec (this can be used as a status signal for a dsp, fpga or other microcontroller). the pdos can be programmed to pull- up to a number of different options. the outputs can be programmed as:C ? open drain (allowing the user to connect an external pull-up resistor) ? open drain with weak pull-up to vdd ? push pull to vdd ? open-drain with weak pull-up to vpn ? push-pull to vpn ? strong pull-down to gnd ? internally charge- pumped high drive (12v- pdo 1- 6 only) the last option (available only on pdos 1 to 6) allows the user to directly drive a voltage high enough to fully enhance an external n-fet which is used to isolate, for example, a card-side voltage from a backplane supply (a pdo will sustain greater than 10.5v into a 1a load). the pull-down switches may be used to drive status leds. the data driving each of the pdos can come from one of three sources. the source can be enabled in the pnpdocfg configuration register (refer to an-698). the data sources are: ? an output from the se. ? directly from the smbus. a pdo can be configured so that the smbus has direct control over it. this enables software control of the pdos. thus, a microcontroller could be used to initiate a software power-up/power-down sequence. ? an on- chip clock. a 100khz clock is generated on the device. this clock can be made available on any of the pdos. it could be used to clock an external device such as a led, for example. the default condition of the pdos is to be pulled to gnd by a weak (20k?) on-chip pull-down resistor. this is also the condition of the pdos on power-up until the configuration is downloaded from eeprom and the programmed setup is latched. the outputs are actively pulled low once there is a supply 1v or greater on vpn or vh. the outputs remain high impedance prior to 1v appearing on vpn or vh. this provides a known condition for the pdos during power-up. the internal pull-down can be overdriven with an external pull-up of suitable value tied from the pdo pin to the required pullup voltage. the 20k? resistor must be accounted for in calculating a suitable value. for example, if it was required to pull pdon up to 3.3v, and 5v was available as an external supply, the pull-up resistor value is given by:- ( ) ? + ? = k 20 r k 20 v 5 v 3 3 up . therefore, ( ) ? = ? ? ? = k 10 3 3 k 66 k 100 r up .
preliminary technical data ADM1066 rev. prl| page 17 of 32 figure 28. programmable driver output
ADM1066 preliminary technical data rev. prl | page 18 of 32 ADM1066 sequencing engine the ADM1066 incorporates a sequencing engine (se) which provides the user with powerful and flexible control of sequencing. the se implements a state machine control of the pdo outputs, with state changes conditional on input events. se programs can enable complex control of boards, such as powerup and power down sequence control, fault event handling, interrupt generation on warnings etc. a watchdog function, to verify the continued operation of a processor clock, can be integrated into the se program. the se can also be controlled via the smbus, giving software or firmware control of the board sequencing considering the function of the se from an applications viewpoint it is most instructive to think of the se as providing a state for a state machine. this state has the following attributes: ? it is used to monitor signals indicating the status of the 10 input pins, vp1-4, vh and vx1-vx5 ? it can be entered from any other state ? there are three exit routes which move the state machine on to a next state, these are: 1. end of step detection 2. monitoring fault 3. timeout ? delay timers for the end of step and timeout blocks above can be programmed independently and will change with each state change. the range of timeouts is from 0ms to 400ms ? the output condition of the 10 pdo pins is defined and fixed within a state ? the transition from one state to the next is made in less than 20s. this is the time taken to download a state definition from eeprom to the se. figure 29. state cell the ADM1066 offers up to 63 such state definitions. the signals being monitored to indicate the status of the input pins are the outputs of the sfds. warnings the se is also monitoring the warnings. these are generated by adc readings violating their limit register value or by the secondary voltage monitors on vp1-4, vh. these are all ored together and available as a single warnings input to each of the three blocks which enable exiting from a state. sw flow-unconditional jump the se can be forced to advance to the next state unconditionally. this enables the user to force the se to advance. examples where this might be used include moving to a margining state or as a method of debugging a sequence. the sw flow or go to command can be seen as another input to end of step and timeout blocks which provide an exit from each state. table 6. example sequence states entries state end of step timeout monitor idle1 if vx1 is low then go to state idle2 idle2 if vp1 is ok then go to state en3v3 en3v3 if vp2 is ok then go to state en2v5 if vp2 is not ok after 10ms then goto state dis3v3 if vp1 is not ok then goto state idle1 dis3v3 if vx1 is high then go to state idle1 en2v5 if vp3 is ok then go to state pwrgd if vp3 is not ok after 20ms then goto state dis2v5 if vp1 or vp2 is not ok then goto state fsel2 dis2v5 if vx1 is high the go to state idle1 fsel1 if vp3 is not ok then go to state dis2v5 if vp1 or vp2 is not ok then goto state fsel2 fsel2 if vp2 is not ok then go to state dis3v3 if vp1 is not ok then goto state idle1 pwrgd if vx1 is high then go to state dis2v5 if vp1 or vp2 or vp3 is not ok then goto state fsel1
preliminary technical data ADM1066 rev. prl| page 19 of 32 sequencing engine application example an example application will be considered here to demonstrate the operation of the se. figure 28 below shows how the simple building block of a single se state can be used to build up a power-up sequence for a 3Csupply system. table 6 below textually describes the same se implementation. in this system the presence of a good 5v supply on vp1, and the vx1 pin being held low, are the trigger required for an up sequence to start. the sequence intends to turn on the 3.3v supply next, then the 2.5v supply (assuming successful turn-on of the 3.3v supply). once all 3 supplies are good the pwrgd state is entered, where the se will remain until a fault occurs on one of the 3 supplies, or it is instructed to go through a power-down sequence by vx1 going high. faults are dealt with on the way through the up sequence on a case-by case basis. the text below which describes the individual blocks will use the example application to demonstrate what the state machine is doing. figure 30. flow diagram figure 31. pdo outputs for each state end of step detector this block is used to detect when a step in a sequence has been completed. it is simply looking for one of the inputs to se to change state and is most often used to be the gate on successful progress through an up or down sequence. a timer block is included, in this detector- it can be thought of as a way to insert delays into an up or down sequence, if required. timer delays can be set from 10s to 400ms. figure 32 shows a block diagram of the end of step detector. figure 32. end-of-step detector it is also possible to use the end of step detector to help identify monitoring faults. in the example application shown in figure 30 it can be seen how the fsel1 and fsel2 states are being used to identify which of vp1,vp2 or vp3 has faulted and to take the appropriate action. monitoring fault detector this block is used to detect a failure on any one of a number of inputs. the logical function implementing this is a wide or gate which is used to detect when any one of a number of inputs deviates from its expected condition. the clearest demonstration of the use of this block is in the pwrgd state where the monitor block will indicate that a failure on any one of the vp1,vp2 and vp3 inputs has occurred. there is no programmable delay available in this block. this is because, the triggering of a fault condition is likely to be caused by a supply falling out of tolerance, a situation to which the user will want to react to as quickly as possible. there is some latency in moving out of this state, however, since it takes a finite time (~20s) for the state configuration to download from eeprom into the se. figure 33 below shows a block diagram of the monitoring fault detector.
ADM1066 preliminary technical data rev. prl | page 20 of 32 figure 33. monitoring fault detector timeout detector this block is included to allow the user to trap a failure to make proper progress through an up or down sequence. in the example application we can see the timeout next state transition being used from the en3v3 and en2v5 states. in the case of the en3v3 state, the signal 3v3on is asserted on entry to this state (on the pdo1 output pin) to turn on a 3.3v supply. this supply rail is connected to the vp2 pin and the end of step detector is looking for the vp2 to go good (going above its uv threshold, which will be set on the supply fault detector (sfd) attached to that pin). progress forward in the up sequence is made when this change is detected. if, however, the supply failed to go good C perhaps because of a short circuit over-loading this supply C then the timeout block allows this problem to be trapped. in the example shown, if the 3.3v supply does not go good within 10ms then the se moves to the dis3v3 state and turns off this supply by bringing pdo1 low. it also indicates that a fault has occurred by taking pdo3 high. timeout delays of between 0s and 400ms can be programmed. closed loop supply margining it is often necessary for the system designer to be able to adjust supplies, either to optimize their level, or to force them away from nominal values to characterize the system performance under these conditions. this is a function typically performed at in- circuit test (ict), for instance, where the manufacturer wishes to guarantee that the product under test functions correctly at, say, nominal supplies ?10%. the ADM1066 incorporates all the circuits required to do this, with a 12-bit successive approximation adc to read back the level of any of the supervised voltages, and six voltage output dacs (dac1C dac6) which can be used to adjust supply levels. these circuits can be used along with some other intelligence such as a microcontroller to implement a closed loop margining system which will allow any dc-dc supply to be set to any voltage, accurate to within 0.5% of the target. mux adc dac device controller (smbus) m controller dc/dc converter output feedback gnd attenuation resistor, r3 pcb trace noise decoupling cap adm1062 vin vh/vpn/vxn dacoutn r1 r2 figure 34. closed loop margining system using ADM1066 the simplest circuit to implement this function is an attenuation resistor to connect the dacn pin to the feedback node of a dc-dc converter. when the dacn output voltage is set equal to the feedback voltage, no current is flowing in the attenuation resistor and the dc-dc output voltage will not change. taking dacn above the feedback voltage forces current into the feedback node and the output of the dc-dc converter will be forced to fall to compensate for this. the dc-dc output can be forced high by setting the dacn output voltage lower than the feedback node voltage. the series resistor can be split in two and the node between them decoupled with a capacitor to ground. this will help to decouple any noise picked up from the board. decoupling to a ground local to the dc-dc converter is recommended. then the simplest algorithm to implement closed loop margining is as follows: 1. disable the six dacn outputs. 2. set dac output voltage equal to the voltage on the feedback node. 3. enable the dac. 4. read the voltage at the dc-dc output (which will be connected to one of the vp1C4,vh or vx1C5 pins). 5. if necessary, modify the dacn output code up or down to adjust the dc-dc output voltage, otherwise, stop since target voltage has been reached. 6. set the dac output voltage to a value which alters the supply output by the required amount (eg) 5%. 7. repeat from 4. steps 1-3 ensure that when the dacn output buffer is turned on it has very little effect on the dc-dc output. the dac output buffer has been designed to power up without glitching. it does this by first powering up the buffer to follow the pin voltage and
preliminary technical data ADM1066 rev. prl| page 21 of 32 does not drive out on to the pin at this time. once the output buffer is properly enabled, the buffer input is switched over to the dac, and the output stage of the buffer is turned on. output glitching is negligible. writing to the dacs four dac ranges are offered and these are placed with mid- code (code 0x7f) at 0.6v, 0.8v, 1.0v and 1.25v. these voltages are placed to correspond to the most common feedback voltages. centering the dac outputs in this way provides the best use of the dac resolution i.e. for most supplies it will be possible to place the dac mid-code at the point where the dc-dc output is not modified, thus giving a full half of the dac range to margin up and and the other half to margin down. the dac output voltage is set by the code written to the dacn register. the voltage is linear with the unsigned binary number in this register. the code 0x7f is placed at the mid-code voltage as described above. the output voltage is given by the following equation: ( ) off v 6015 0 255 f 7 x 0 dacn output dac + ? ? = . where v off is one of the four offset voltages described above. choosing the size of the attenuation resistor the full output swing of the dacs is +/-300mv around whichever of the four mid code voltages is selected. the voltage range for each midcode voltage is shown in table x below. table 6. margining dacs- midcode, max and min voltages mid code voltage minimum voltage output maximum voltage output 0.6v 0.3v 0.9v 0.8v 0.5v 1.1v 1.0v 0.7v 1.3v 1.25v 0.95v 1.55v how much this dac voltage swing affects the output voltage of the dc/dc converter being margined is determined by the size of the attenuation resistor, r3 (see figure 34). since the voltage at the feedback pin remains constant, , the current flowing from the feedback node to gnd via r2 is a constant. also, the feedback node itself is high impedance. this means that the current flowing through r1 is the same as the current flowing through r3. therefore, there is a direct relationship between the extra voltage drop across r1 during margining and the voltage drop across r3. this relationship is given by the equation () dacout fb out v v r r v ? = ? 3 1 where, ev out = the change in v out ` v fb = the voltage at the feedback node of the dc/dc converter v dacout = the voltage output of the margining dac from this equation it can be seen that if the user wishes for the output voltage to change by +/-300mv, then r1=r3. if the user wishes for the output voltage to change by +/-600mv then r1=2xr3 etc. it is best to use the full dac output range to margin a supply. choosing the attenuation resistor in this way provides the most resolution out of the dac C in other words, with one dac code change the smallest effect on the dc-dc output voltage is induced. if the resistor is sized up to use code,say , 27(dec) to 227(dec) to move the dc-dc output by 5%, then that is 100 codes to move 5% i.e. each code moves the output by 0.05%. this is beyond the readback accuracy of the adc but shouldnt prevent the user building their circuit to use the most resolution. dac limiting/other safety features limit registers (called dplimn and dnlimn) on the device offer the user some protection from firmware bugs which could cause catastrophic board problems by forcing supplies beyond their allowable output ranges. essentially the dac code written into the dacn register is clipped such that the code used to set the dac voltage is actually given by dac code = dacn, dacn dnlimn and dacn dplimn = dnlimn, dacn < dnlimn = dplimn, dacn > dplimn in addition, the dac output buffer is tri-stated if dnlimn > dplimn. in this way it is possible for the user to make it very difficult for the dac output buffers to be turned on at all in normal system operation by programming the limit registers in this way (these are among the registers downloaded from eeprom at startup).
ADM1066 preliminary technical data rev. prl | page 22 of 32 communicating with the ADM1066 configuration downlo ad at power-up the configuration of the ADM1066C the uv/ov thresholds, glitch filter timeouts, pdo configurations etc, is dictated by the contents of ram. the ram is comprised of digital latches which are local to each of the functions on the device. the latches are double buffered and actually comprised of two identical latches, latch a and latch b. thus, the update of a function first updates the contents of latch a and then updates the contents of latch b with identical data. the advantage of the architecture is explained in detail below. these latches are volatile memory and lose their contents at power- down. therefore, at power- up the configuration in the ram must be restored. this is achieved by downloading the contents of the eeprom (non- volatile memory) to the local latches. this download occurs in a number of steps. 1. with no power applied to the device, the pdos are all high impedance. 2. once 1v appears on any of the inputs connected to the vdd arbitrator (vh or vpn), the pdos are all weakly pulled to gnd with a 20k? impedance. 3. once the supply rises above the under voltage lockout of the device (uvlo is 2.5v), the eeprom starts to download to the ram. 4. the eeprom downloads its contents to all latch as. 5. once the contents of the eeprom are completely downloaded to latch as, the device controller signals all latch as to download to all latch bs simultaneously, thus completing the configuration download. 6. 0.5ms after the configuration download, the first state definition is downloaded from eeprom into the sequencing engine noteC any attempt to communicate with the device prior to this download completion will result in a nack being issued from the ADM1066. updating the configuration of the ADM1066 once powered up, with all of the configuration settings loaded from eeprom into the ram registers, the user may wish to alter the configuration of functions on the ADM1066 (eg) change the uv or ov limit of an sfd, change the fault output of an sfd, change the rise time delay of one of the pdos etc. the ADM1066 provides a number of options which allow the user to update the configuration differently over the smbus interface. all of these options are controlled in the register updcfg. the options are: 1. update the configuration in real time. the user writes to ram across the smbus and the configuration is updated immediately. 2. update a latches without updating the b latches. with this method, the configuration of the ADM1066 will remain unchanged and continue to operate in the original setup until the instruction is given to update the b latches. 3. change eeprom register contents without changing the ram contents, and then download the revised eeprom contents to the ram registers. again, with this method, the configuration of the ADM1066 will remain unchanged and continue to operate in the original setup until the instruction is given to update the ram. the instruction to download from the eeprom in option 3 above is also a useful way to restore the original eeprom contents if revisions to the configuration are unsatisfactory. if the user alters, say, an ov threshold they can do this by updating the ram register as described in 1 above. if they are not satisfied with this change and wish to revert to the original programmed value, then the device controller can issue a command to download the eeprom contents to the ram again, thus restoring the ADM1066 to its original configuration. this type of operation is possible because of the topology of the ADM1066. the local (volatile) registers, or ram, are all double buffered latches. setting bit 0 of the updcfg register to 1 leaves the double buffered latches open at all times. if bit 0 is set to 0, then when ram write occurs across the smbus only the first side of the double buffered latch is written to. the user must then write a 1 to bit 1 of the updcfg register. this generates a pulse to update all of the second latches at once. similarly with eeprom writes. a final bit in this register is used to enable eeprom page erasure. if this bit is set high, then the contents of an eeprom page can all be set to 1. if low, then the contents of a page cannot be erased, even if the command code for page erasure is programmed across the smbus. the bitmap for register updcfg is shown in an-698. a flow chart for download at power up and subsequent configuration updates is shown in figure 35 overleaf.
preliminary technical data ADM1066 rev. prl| page 23 of 32 figure 35. configuration update flow diagram updating the sequencing engine of the ADM1066 the update of the se functions differently to the regular configuration latches. the se has its own dedicated 512 byte eeprom for storing state definitions, providing 63 individual states with a 64- bit word each (one state is reserved). at power- up, the first state is loaded from the se eeprom into the engine itself. when the conditions of this state are met, the next state is loaded from eeprom into the engine, and so on. the loading of each new state takes approximately 20s. if a state is to be altered, then the required changes must be made directly to eeprom. ram for each state does not exist. the relevant alterations must be made to the 64- bit word, which is then uploaded directly to eeprom. internal registers of the ADM1066 the ADM1066 contains a large number of data registers. a brief description of the principal registers is given below. address pointer register: this register contains the address that selects one of the other internal registers. when writing to the ADM1066, the first byte of data is always a register address, which is written to the address pointer register. configuration registers: provide control and configuration for various operating parameters of the ADM1066. ADM1066 eeprom the ADM1066 has two 512 byte cells of non-volatile, electrically-erasable programmable read-only memory (eeprom), from register addresses f800h to fbffh. this may be used for permanent storage of data that will not be lost when the ADM1066 is powered down, one eeprom cell containing the configuration data of the device, the other containing the state definitions for the sequencing engine. although referred to as read only memory, the eeprom can be written to (as well as read from) via the serial bus in exactly the same way as the other registers. the only major differences between the e 2 prom and other registers are: 1. an eeprom location must be blank before it can be written to. if it contains data, it must first be erased. 2. writing to eeprom is slower than writing to ram. 3. writing to the eeprom should be restricted because it has a limited write/cycle life of typically 10,000 write operations, due to the usual eeprom wear-out mechanisms. the first eeprom is split into 16 (0 to 15) pages of 32 bytes each. pages 0 to 6, starting at address f800, hold the configuration data for the applications on the ADM1066 (the sfds, pdos etc.). these eeprom addresses are the same as the ram register addresses, prefixed by f8. page 7 is reserved. pages 8 to 15 are for customer use. data can be downloaded from eeprom to ram in one of two ways:C 1. at power- up, pages 0 to 6 are downloaded. 2. setting bit 0 of the udownld register (d8h) performs a user download of pages 0 to 6.
ADM1066 preliminary technical data rev. prl | page 24 of 32 serial bus interface control of the ADM1066 is carried out via the serial system management bus (smbus). the ADM1066 is connected to this bus as a slave device, under the control of a master device. it takes approximately 1ms after power up for the ADM1066 to download from it's eeprom. therefore access is restricted to the ADM1066 until the download is completed. identifying the ADM1066 on the smbus the adm1060 has a 7-bit serial bus slave address. when the device is powered up, it will do so with a default serial bus address. the five msb's of the address are set to 01101, the two lsb's are determined by the logical states of pin a1 and a0. this allows the connection of 4 ADM1066s to the one smbus. the device also has a number of identification registers (read only) which can be read across the smbus. table 7 lists these registers, their values, and functions. table 7. name address value function manid f4h 41h manufacturer id for analog devices revid f5h --h silicon revision mark1 f6h --h s/w brand mark2 f7h --h s/w brand general smbus timing figure 36, figure 37 and figure 38 show timing diagrams for general read and write operations using the smbus. the smbus specification defines specific conditions for different types of read and write operation, which are discussed later. the general smbus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, defined as a high to low transition on the serial data line sda whilst the serial clock line scl remains high. this indicates that a data stream will follow. all slave peripherals connected to the serial bus respond to the start condition, and shift in the next 8 bits, consisting of a 7-bit slave address (msb first) plus a r/ w bit, which determines the direction of the data transfer, i.e. whether data will be written to or read from the slave device (0 = write, 1 = read). the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. all other devices on the bus now remain idle whilst the selected device waits for data to be read from or written to it. if the r/ w bit is a 0 then the master will write to the slave device. if the r/ w bit is a 1 the master will read from the slave device. 2. data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an acknowledge bit from the slave device. data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a stop signal. if the operation is a write operation, the first data byte after the slave address is a command byte. this tells the slave device what to expect next. it may be an instruction such as telling the slave device to expect a block write, or it may simply be a register address that tells the slave where subsequent data is to be written. since data can flow in only one direction as defined by the r/ w bit, it is not possible to send a command to a slave device during a read operation. before doing a read operation, it may first be necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. 3. when all data bytes have been read or written, stop conditions are established. in write mode, the master will pull the data line high during the 10th clock pulse to assert a stop condition. in read mode, the master device will release the sda line during the low period before the 9th clock pulse, but the slave device will not pull it low. this is known as no acknowledge. the master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition smbus protocols for ram and eeprom the ADM1066 contains volatile registers (ram) and non- volatile eeprom. user ram occupies address locations from 00h to dfh, whilst eeprom occupies addresses from f800h to fbffh. data can be written to and read from both ram and eeprom as single data bytes. data can only be written to unprogrammed eeprom locations. to write new data to a programmed location it is first necessary to erase it. eeprom erasure cannot be done at the byte level, the eeprom is arranged as 32 pages of 32 bytes, and an entire page must be erased. page erasure is enabled by setting bit 2 in register updcfg (address 90h) to 1. if this is not set then page erasure cannot occur, even if the command byte (feh) is programmed across the smbus.
preliminary technical data ADM1066 rev. prl| page 25 of 32 figure 36. general smbus write timing diagram figure 37. general smbus read timing diagram figure 38. diagram for serial bus timing
ADM1066 preliminary technical data rev. prl | page 26 of 32 ADM1066 write operations the smbus specification defines several protocols for different types of read and write operations. the ones used in the ADM1066 are discussed below. the following abbreviations are used in the diagrams: s C start p C stop r C read w C write a C acknowledge a C no acknowledge the ADM1066 uses the following smbus write protocols: send byte in this operation the master device sends a single command byte to a slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master asserts a stop condition on sda and the transaction ends. in the ADM1066, the send byte protocol is used for two purposes. 1. to write a register address to ram for a subsequent single byte read from the same address or block read or write starting at that address. this is illustrated in figure 39 . figure 39. setting a ram address for subsequent read 2. erase a page of eeprom memory. eeprom memory can be written to only if it is unprogrammed. before writing to one or more eeprom memory locations that are already programmed, the page or pages containing those locations must first be erased. eeprom memory is erased by writing a command byte. the master sends a command code that tells the slave device to erase the page. the ADM1066 command code for a pages(s) erasure is feh (11111110). note that, in order for page erasure to take place, the page address has to be given in the previous write word transaction (see write byte below). also, bit 2 in register updcfg (address 90h) must be set to 1. figure 40. eeprom page erasure as soon as the ADM1066 receives the command byte, page erasure begins. the master device can send a stop command as soon as it sends the command byte. page erasure takes approximately 20ms. if the ADM1066 is accessed before erasure is complete, it will respond with a nack. write byte/word in this operation the master device sends a command byte and one or two data bytes to the slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master sends a data byte. 7. the slave asserts ack on sda. 8. the master sends a data byte (or may assert stop at this point). 9. the slave asserts ack on sda. 10. the master asserts a stop condition on sda to end the transaction. in the ADM1066, the write byte/word protocol is used for three purposes. 1. write a single byte of data to ram. in this case the command byte is the ram address from 00h to dfh and the (only) data byte is the actual data. this is illustrated in figure 41 figure 41. single byte write to ram 2. set up a two byte eeprom address for a subsequent read, write, block read, block write or page erase. in this case the command byte is the high byte of the eeprom address
preliminary technical data ADM1066 rev. prl| page 27 of 32 from f8h to fbh. the (only) data byte is the low byte of the eeprom address. this is illustrated in figure 42. figure 42. setting an eeprom address note for page erasure that as a page consists of 32 bytes only the three msbs of the address low byte are important. the lower 5 bits of the eeprom address low byte only specify addresses within a page and are ignored during an erase operation. 3. write a single byte of data to eeprom. in this case the command byte is the high byte of the eeprom address from f8h to fbh. the first data byte is the low byte of the eeprom address and the second data byte is the actual data. this is illustrated in figure 43 figure 43. single byte write to eeprom block write in this operation the master device writes a block of data to a slave device. the start address for a block write must previously have been set. in the case of the ADM1066 this is done by a send byte operation to set a ram address or a write byte/word operation to set an eeprom address. 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code that tells the slave device to expect a block write. the ADM1066 command code for a block write is fch (11111100). 5. the slave asserts ack on sda. 6. the master sends a data byte that tells the slave device how many data bytes will be sent. the smbus specification allows a maximum of 32 data bytes to be sent in a block write. 7. the slave asserts ack on sda. 8. the master sends n data bytes. 9. the slave asserts ack on sda after each data byte. 10. the master asserts a stop condition on sda to end the transaction. figure 44. block write to eeprom or ram unlike some eeprom devices which limit block writes to within a page boundary, there is no limitation on the start address when performing a block write to eeprom, except: 1. there must be at least n locations from the start address to the highest eeprom address (fbffh), to avoiding writing to invalid addresses. 2. if the addresses cross a page boundary, both pages must be erased before programming. note that the ADM1066 features a clock extend function for writes to eeprom. programming an eeprom byte takes approximately 250s, which would limit the smbus clock for repeated or block write operations. the ADM1066 pulls scl low and extends the clock pulse when it cannot accept any more data. ADM1066 read operations the ADM1066 uses the following smbus read protocols: receive byte in this operation the master device receives a single byte from a slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the read bit (high). 3. the addressed slave device asserts ack on sda. 4. the master receives a data byte. 5. the master asserts no ack on sda. 6. the master asserts a stop condition on sda and the transaction ends. in the ADM1066, the receive byte protocol is used to read a single byte of data from a ram or eeprom location whose address has previously been set by a send byte or write byte/word operation. this is illustrated in figure 45. figure 45. single byte read from eeprom or ram
ADM1066 preliminary technical data rev. prl | page 28 of 32 block read in this operation the master device reads a block of data from a slave device. the start address for a block read must previously have been set. in the case of the ADM1066 this is done by a send byte operation to set a ram address, or a write byte/word operation to set an eeprom address. the block read operation itself consists of a send byte operation that sends a block read command to the slave, immediately followed by a repeated start and a read operation that reads out multiple data bytes, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code that tells the slave device to expect a block read. the ADM1066 command code for a block read is fdh (11111101). 5. the slave asserts ack on sda. 6. the master asserts a repeat start condition on sda. 7. the master sends the 7-bit slave address followed by the read bit (high). 8. the slave asserts ack on sda. 9. the ADM1066 sends a byte count data byte that tells the master how many data bytes to expect. the ADM1066 will always return 32 data bytes (20h), which is the maximum allowed by the smbus 1.1 specification. 10. the master asserts ack on sda. 11. the master receives 32 data bytes. 12. the master asserts ack on sda after each data byte. 13. the master asserts a stop condition on sda to end the transaction. figure 46. block read from eeprom or ram error correction the ADM1066 provides the option of issuing a pec (packet error correction) byte after a write to ram, a write to eeprom, a block write to ram/eeprom or a block read from ram/eeprom. this enables the us er to verify that the data received by or sent from the ADM1066 is correct. the pec byte is an optional byte sent after that last data byte has been written to or read from the ADM1066. the protocol is as follows:C 1. the ADM1066 issues a pec byte to the master. the master should check the pec byte and issue another block read if the pec byte is incorrect. 2. a nack is generated after the pec byte to signal the end of the read. note: the pec byte is calculated using crc-8. the frame check sequence (fcs) conforms to crc-8 by the polynomial:C () 1 x x x x c 1 2 8 + + + = consult smbus 1.1 specification for more information. an example of a block read with the optional pec byte is shown in figure 47 below. figure 47. block read from eeprom or ram with pec
preliminary technical data ADM1066 rev. prl| page 29 of 32 outline dimensions figure 48. 40-lead 66 chip scale package (cp-40) dimensions shown in millimeters figure 49. 48-lead 77 tqfp package (su-48) dimensions shown in millimeters
ADM1066 preliminary technical data rev. prl | page 30 of 32 ordering guide model temperature range package description package option ADM1066acp-u3 ?40c to +85c 40-lead lfcsp cp-40 ADM1066asu-u3 ?40c to +85c 48-lead tqfp su-48
preliminary technical data ADM1066 rev. prl| page 31 of 32 notes
ADM1066 preliminary technical data rev. prl | page 32 of 32 notes ? 2003 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners.

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